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HD151TS207SS
2
I
C Controlled Register Bit Map
Byte0 Control Register
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
PCI_Stop Reflects the current value
of the external PCI_STOP# pin
2
Reserved
1
FS_B Reflects the value of the
FS_B pin sampled on power up
0
FS_A Reflects the value of the
FS_A pin sampled on power up
Table1 Clock Frequency Function Table
Byte6
FS_A
FS_B
Bit5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table2 Test Clock select table
TEST_CLK# CPU
[MHz]
1
REF/2
0
Hi–Z
Note:
1. REF is a clock over driven on the XIN during test mode.
Rev.1.00, Apr.25.2003, page 7 of 38
Contents
0 = PCI_STOP# pin is Low
1 = PCI_STOP# pin is High
0 = FS_B Low at power up
1 = FS_B High at power up
0 = FS_A Low at power up
1 = FS_A High at power up
CPU
SRC
[MHz]
[MHz]
100
100/200
200
100/200
133
100/200
166
100/200
200
100/200
400
100/200
266
100/200
333
100/200
SRC
3V66
[MHz]
[MHz]
REF/2
REF/4
Hi–Z
Hi–Z
3V66
PCIF
REF0
[MHz]
PCI
REF1
[MHz]
[MHz]
66
33
14.318
66
33
14.318
66
33
14.318
66
33
14.318
66
33
14.318
66
33
14.318
66
33
14.318
66
33
14.318
PCIF
REF0
PCI
REF1
[MHz]
[MHz]
REF/8
REF
Hi–Z
Hi–Z
Type
Default
Note
R
0
R
0
R
0
R
0
R
X
R
X
R
X
See
Table
1
R
X
USB
Note
DOT
[MHz]
48
48
48
48
48
48
48
48
USB
Note
DOT
[MHz]
REF/2
See Note1,
Table3
Hi–Z
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