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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Byte12 Control Register
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
PLL1 Output (VCO1) Frequency
Control Bit
(M1/N1 Divider Control Bit)
PLL1 : for SRC/3V66/PCI_PLL
1
PLL1 N1 Divider Control Bit9
0
PLL1 N1 Divider Control Bit8
Note:
1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Byte13 Control Register
Bit
Description
7
PLL1 N1 Divider Control Bit7
6
PLL1 N1 Divider Control Bit6
5
PLL1 N1 Divider Control Bit5
4
PLL1 N1 Divider Control Bit4
3
PLL1 N1 Divider Control Bit3
2
PLL1 N1 Divider Control Bit2
1
PLL1 N1 Divider Control Bit1
0
PLL1 N1 Divider Control Bit0
Note:
1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Rev.1.00, Apr.25.2003, page 15 of 38
Contents
0 = Normal mode
PLL1 M1[6:0] and N1[9:0] are
changed on Table 5 selection
decided by FS4/3/2/A/B or
B9[5:1]
1 = Over or Down clocking mode
PLL1 M1[6:0] and N1[9:0] are
changed by B12[1:0], B13[7:0]
and B14[6:0].
B12[1:0], B13[7:0] and B14[6:0]
are able to be changed at B12[2]
= 1.
N1[9]
N1[8]
Contents
N1[7]
N1[6]
N1[5]
N1[4]
N1[3]
N1[2]
N1[1]
N1[0]
Type
Default
Note
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
See.
Note
1
R/W
0
R/W
0
Type
Default
Note
R/W
0
See
Note
R/W
1
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
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