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HD151TS207SS
Clock Stop Timing Diagram
PCI_STOP# Assertion/De-assersion
PCI_STOP#
PCI_F
PCI
SRC (Stoppable)
SRC (Stoppable)
SRC# (Stoppable)
PWRDWN# Assertion/De-assersion
PWRDWN#
CPU (Stoppable)
CPU (Stoppable)
CPU# (Stoppable)
PWRDWN# Functionality
PWRDWN#
1
0
Rev.1.00, Apr.25.2003, page 24 of 38
6 Iref (Controled by Byte2[6])
Tristate (Controled by Byte2[6])
PCI_STOP# Assertion/De-assertion Waveforms
2 Iref (Controled by Byte2[5:3])
Float (Controled by Byte2[5:3])
Float
PWRDWN# Assertion/De-assertion Waveforms
CPU
CPU#
SRC
SRC#
Normal
Normal Normal
Normal
Iref:2
Iref:2
Float
Float
or Float
or Float
Low
Tristate
< 1.8 ms
6 Iref
6 Iref
3V66
PCIF/PCI
USB/DOT
66MHz
33MHz
48MHz
Low
Low
Low
REF
14.318MHz
Low
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