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HD151TS207SS
Clock Out
Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output)
Clock Outx
Clock Outy
Fig.2 Output Clock Skew (3.3V Single Ended Clock Output)
CPU
TS207
CPU#
R
=
I(ref)
475 Ω
Rev.1.00, Apr.25.2003, page 36 of 38
tcycle n
t
= (tcycle n) - (tcycle n+1)
CCS
1.5 V
1.5 V
tskS
Z
LT
= 33.2 Ω
R
S
= 33.2 Ω
R
S
R
=
R
=
P
P
49.9 Ω
49.9 Ω
Fig.3 Load Circuit for CPU/CPU#
tcycle n+1
= 50 Ω
= Z
LC
LT
LC
C
= 2 pF
L
C
= 2 pF
L
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