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HD151TS207SS
Pin Descriptions (cont.)
Pin name
No.
PWRDWN#/
21
SAFE_F#
3V66_0/RESET#
22
3V66_[1:3]
23,26,
27
SCLK
28
**SEL66_48/
29
3V66_4/VCH
SDATA
30
**SEL48_24/
31
USB_48
FS3/DOT_48
32
VTT_PWRGD#
35
SRC#
37
SRC
38
CPU_[0:2]#
40,43,
46
CPU_[0:2]
41,44,
47
PCI_STOP#
49
TEST_CLK#
50
FS_[A:B]
51,52
IREF
52
Note:
(*):
Those pins are 150 k internal pulled-UP.
(**):
Those pins are 150 k internal pulled-DOWN
Rev.1.00, Apr.25.2003, page 5 of 38
Type
Description
INPUT
PWRDWN# / SAFE_F# selectable input.
PULL–UP*
Default is PWRDWN# input.
Byte15[5] = "1" : SAFE_F# input.
PWRDWN# is all clocks stop pin.
Asynchronous active "Low" input.
When asserted low, all output clocks are disabled.
SAFE_F# is active "Low" input.
When SAFE_F# is "Low" ,frequency mode is changed to the
predefined frequency mode.
OUTPUT
3V66 / Watchdog RESET# selectable output.
Default is 3V66 output.
This signal is active low and selected by Mode latch input.
OUTPUT
3V66 clock 3.3V outputs.
INPUT
Clock input for I
PULL-UP*
INPUT/
Latched select input for 3V66/VCH output 1 = 48 MHz,
OUTPUT
0 = 66.66 MHz. /3V66 or VCH clock output.
IN/OUTPUT
Data input for I
PULL-UP*
INPUT/
Latched select input for 48_24 MHz output
OUTPUT
1 = 24 MHz, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.
INPUT/
Frequency select latch input pin.
OUTPUT
/DOT_48 clock 3.3 V output.
INPUT
Qualifying input that latches FS_A and FS_B.
PULL-UP*
When asserted low, FS_A and FS_B are latched.
OUTPUT
"Complementary" clock of Differential Serial Reference Clock.
OUTPUT
"True" clock of Differential Serial Reference Clock.
OUTPUT
"Complementary" clock of differential CPU clock.
OUTPUT
"True" clock of differential CPU clock.
INPUT
PCI clocks stop pin. Active "Low" input.
PULL–UP*
When asserted low, PCI[6:0] and SRC clocks are
synchronously disabled in low state.
Usually this pin does not give to effect PCIF[2:0] clock outputs.
INPUT
Test clock mode pin. Active "Low" input.
PULL-UP*
INPUT
CPU clocks frequency select latch input.
INPUT
A precision resistor is attached to this pin which is connected
to internal current reference.
A resistor is connected between this pin and GNDIREF.
2
C logic.
2
C logic.
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