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Renesas HD151TS207SS Specification Sheet page 11

Mother board clock generator for intel p4+ chipset (springdale)

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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Byte7 Vendor Identification Register
Bit
Description
7
Revision Code Bit3
6
Revision Code Bit2
5
Revision Code Bit1
4
Revision Code Bit0
3
Vendor ID Bit3
2
Vendor ID Bit2
1
Vendor ID Bit1
0
Vendor ID Bit0
Byte8 Read Back Byte Count Register
Bit
Description
7
Read back byte count Bit7
6
Read back byte count Bit6
5
Read back byte count Bit5
4
Read back byte count Bit4
3
Read back byte count Bit3
2
Read back byte count Bit2
1
Read back byte count Bit1
0
Read back byte count Bit0
Rev.1.00, Apr.25.2003, page 11 of 38
Contents
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Contents
Writing to this register will configure
byte Count and how many bytes will
be read back.
Default is 1Ehex = 30 bytes.
Type
Default
Note
R
0
R
0
R
0
R
1
R
1
R
1
R
1
R
1
Type
Default
Note
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
0

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