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HD151TS207SS
Renesas clock generator I
2. Read mode
2.1 Controller (host) sends a start bit.
2.2 Controller (host) sends the write address D2 (h).
2.3 Renesas clock generator will acknowledge (Renesas clock gen. sends "Low").
2.4 Controller (host) sends a begin byte M.
2.5 Renesas clock generator will acknowledge (Renesas clock gen. sends "Low").
2.6 Controller (host) sends a restart bit.
2.7 Controller (host) sends the read address D3 (h).
2.8 Renesas clock generator will acknowledge (Renesas clock gen. sends "Low").
2.9 Renesas clock generator will send the byte count N.
2.10 Controller (host) will acknowledge.
2.11 Renesas clock generator will send data from byte M to byte M+N–1.
2.12 When Renesas clock generator sends the last byte, controller (host) will not acknowledge.
2.13 Controller (host) sends a stop bit.
1 bit
7 bits
Slave
Start bit
address
1 bit
8 bits
Ack
Begin Count = N
Notes: 1. Renesas clock generator is a slave/receiver, I
the latches for the verification.
2.
The data transfer rate supported by this clock generator is 100k bits/sec or less (standard
mode).
3.
The input is operating at 3.3 V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
the controller.
6.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The data is loaded until a stop sequence is
issued.
7.
At power-on, all registers are set to a default condition, as shown.
Rev.1.00, Apr.25.2003, page 26 of 38
2
C Serial Interface Operation (cont.)
1 bit 1 bit
8 bits
R/W
Ack
Begin Byte = M
D2(h)
1 bit
8 bits
1 bit
8 bits
Ack
Byte M
Ack
Byte M+1
2
C interface, the protocol is set to use only block-write from
1 bit
1 bit
7 bits
Slave
Ack
Restart bit
address
1 bit
8 bits
Ack
Byte M+N–1
2
C component. It can read back the data stored in
1 bit
R/W
D3(h)
1 bit
1 bit
Not Ack
Stop bit
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