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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Byte14 Control Register
Bit
Description
7
Reserved
6
PLL1 M1 Divider Control Bit6
5
PLL1 M1 Divider Control Bit5
4
PLL1 M1 Divider Control Bit4
3
PLL1 M1 Divider Control Bit3
2
PLL1 M1 Divider Control Bit2
1
PLL1 M1 Divider Control Bit1
0
PLL1 M1 Divider Control Bit0
Note:
1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Byte15 Control Register
Bit
Description
7
PCI_5 Output Frequency Select
Bit
6
USB_48 Output Frequency
Select Bit
5
SAFE_F# Input mode select Bit
4
Clock Divider Control Bit
3
CPU Divider Control Bit3
2
CPU Divider Control Bit2
1
CPU Divider Control Bit1
0
CPU Divider Control Bit0
Rev.1.00, Apr.25.2003, page 16 of 38
Contents
M1[6]
M1[5]
M1[4]
M1[3]
M1[2]
M1[1]
M1[0]
Contents
0 = 33.3 MHz, 1 = 25 MHz
0 = 48MHz, 1 = 24 MHz
0 = PWRDWN# input mode
1 = SAFE_F# input mode
Default is PWRDWN# input.
SAFE_F# is active "Low" input.
When SAFE_F# is "Low",
frequency mode is changed to
the predefined frequency mode.
Predefined frequency mode is
selected by B23[1].
0 = Normal mode
Clock dividers are changed by
Table 5 selection decided B9[5:1]
1 = Over or Down clocking mode
Clock dividers are changed by
B15[3:0] and B16[7:0].
B15[3:0] and B16[7:0] are able to
be changed at B15[4] = 1.
0001 = 1/1,
0111 = 1/7
0010 = 1/2,
1000 = 1/8
0011 = 1/3,
1001 = 1/9
0100 = 1/4,
1010 = 1/10
0101 = 1/5,
1011 = 1/11
0110 = 1/6,
Type
Default
Note
R/W
0
See
Note
R/W
0
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
Type
Default
Note
R/W
0
R/W
0
R/W
0
R/W
0
R/W
X
R/W
X
R/W
X
R/W
X
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