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HD151TS207SS
2
I
C Controlled Register Bit Map (cont.)
Byte16 Control Register
Bit
Description
7
3V66 / PCI / PCIF Divider Control
Bit3
6
3V66 / PCI / PCIF Divider Control
Bit2
5
3V66 / PCI / PCIF Divider Control
Bit1
4
3V66 / PCI / PCIF Divider Control
Bit0
3
SRC Divider Control Bit3
2
SRC Divider Control Bit2
1
SRC Divider Control Bit1
0
SRC Divider Control Bit0
Byte17 Control Register
Bit
Description
7
Reserved
6
Reserved
5
Reserved
4
PLL2 Output (VCO2) Frequency
Control Bit
(M2 / N2 Divider Control Bit)
PLL2 : for CPU
3
VCO2 Frequency Control Bit11
2
VCO2 Frequency Control Bit10
1
VCO2 Frequency Control Bit9
0
VCO2 Frequency Control Bit8
Note:
1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Rev.1.00, Apr.25.2003, page 17 of 38
Contents
3V66 divider ratio =
0010 = 1/2,
0111 = 1/7
0011 = 1/3,
1000 = 1/8
0100 = 1/4,
1001 = 1/9
0101 = 1/5,
1010 = 1/10
0110 = 1/6,
1011 = 1/11
PCI / PCIF divider ratio = 3v66 x
1/2
0001 = 1/1,
0111 = 1/7
0010 = 1/2,
1000 = 1/8
0011 = 1/3,
1001 = 1/9
0100 = 1/4,
1010 = 1/10
0101 = 1/5,
1011 = 1/11
0110 = 1/6
Contents
0 = Normal mode
VCO2 frequency is changed on
Table 5 selection decided by
FS4/3/2/A/B or B9[5:1].
1 = Over or Down clocking mode
VCO2 frequency is changed by
B17[3:0] and B18[7:0] with
decimal.
B17[3:0] and B18[7:0] are able to
be changed at B17[4] = 1.
These bits are 100MHz digit of
VCO2 frequency.
0000 = 0, 0001 = 1 .... 1001 = 9
Type
Default
Note
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Type
Default
Note
R/W
0
R/W
0
R/W
0
R/W
0
See
Note
1
R/W
0
R/W
1
R/W
0
R/W
0
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