Data Modes - Atmel ATmega48/V Preliminary

16.1.4 SPI Status Register – SPSR
16.1.5 SPI Data Register – SPDR
16.2

Data Modes

ATmega48/88/168
166
Bit 7
SPIF WCOL
Read/Write R
Initial Value 0
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATmega48/88/168 is also used for program memory and EEPROM
downloading or uploading. See
Bit 7
MSB
Read/Write R/W
Initial Value X
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
16-3 and Figure 16-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 16-2 and Table 16-3, as done below.
6 5 4
– –
R R R
0 0 0
16-4). This means that the minimum SCK period will be two CPU
page 295 for serial programming and verification.
6 5 4
R/W R/W R/W
X X X
3 2 1
– – –
R R R
0 0 0
3 2 1
R/W R/W R/W
X X X
0
SPI2X SPSR
R/W
0
/4
osc
0
LSB SPDR
R/W
X Undefined
Figure
2545E–AVR–02/05