Download Print this page
Atmel ATmega128 Manual
Atmel ATmega128 Manual

Atmel ATmega128 Manual

8-bit avr microcontroller with 128k bytes in-system programmable flash
Hide thumbs Also See for ATmega128:

Advertisement

Quick Links

Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 128K Bytes of In-System Self-programmable Flash program memory
– 4K Bytes EEPROM
– 4K Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V ATmega128L
– 4.5 - 5.5V ATmega128
Speed Grades
– 0 - 8 MHz ATmega128L
– 0 - 16 MHz ATmega128
BDTIC
www.bdtic.com/ATMEL
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Summary
Rev. 2467RS–AVR–06/08

Advertisement

loading
Need help?

Need help?

Do you have a question about the ATmega128 and is the answer not in the manual?

Questions and answers

Summary of Contents for Atmel ATmega128

  • Page 1 – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V ATmega128L – 4.5 - 5.5V ATmega128 • Speed Grades – 0 - 8 MHz ATmega128L – 0 - 16 MHz ATmega128 Rev. 2467RS–AVR–06/08...
  • Page 2 Overview The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
  • Page 3 ATmega128 Block Diagram Figure 2. Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTF REG. PORTF PORTA REG. PORTA PORTC REG.
  • Page 4 Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications.
  • Page 5 External Interrupt pins 3 - 0 serve as level interrupt only. • USART has no FIFO buffer, so data overrun comes earlier. Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128. Pin Descriptions Digital supply voltage.
  • Page 6 Note: The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled.
  • Page 7 ATmega128 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 51. Shorter pulses are not guaranteed to generate a reset.
  • Page 8 Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. ATmega128/L rev. A - M characterization is found in the ATmega128 Appendix A. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
  • Page 9 ATmega128 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ($FF) Reserved – – – – – – – – Reserved – – – – – – –...
  • Page 10 $05 ($25) ADCH ADC Data Register High Byte $04 ($24) ADCL ADC Data Register Low byte $03 ($23) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 $02 ($22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 ATmega128 2467RS–AVR–06/08...
  • Page 11 ATmega128 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 $00 ($20) PINF PINF7 PINF6 PINF5...
  • Page 12 (V = 1) then PC ← PC + k + 1 BRVS Branch if Overflow Flag is Set None 1 / 2 if (V = 0) then PC ← PC + k + 1 BRVC Branch if Overflow Flag is Cleared None 1 / 2 ATmega128 2467RS–AVR–06/08...
  • Page 13 ATmega128 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks if ( I = 1) then PC ← PC + k + 1 BRIE Branch if Interrupt Enabled None 1 / 2 if ( I = 0) then PC ← PC + k + 1...
  • Page 14 H ← 0 Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None BREAK Break For On-chip Debug Only None ATmega128 2467RS–AVR–06/08...
  • Page 15 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 2. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
  • Page 16 0.75 0.80 TYP 10/5/2001 TITLE DRAWING NO. REV. 2325 Orchard Parkway 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, San Jose, CA 95131 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega128 2467RS–AVR–06/08...
  • Page 17 ATmega128 64M1 Marked Pin# 1 ID SEATING PLANE TOP VIEW 0.08 Pin #1 Corner SIDE VIEW Pin #1 Option A Triangle COMMON DIMENSIONS (Unit of Measure = mm) NOTE SYMBOL Option B 0.80 0.90 1.00 Pin #1 Chamfer – 0.02 0.05...
  • Page 18 Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. F to M • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer •...
  • Page 19 Update-DR. Problem Fix / Workaround – If ATmega128 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain.
  • Page 20 There will no longer exist separate ordering codes for commercial operation range, only industrial operation range. 8. Updated “Errata” on page Merged errata description for rev.F to rev.M in “ATmega128 Rev. F to M”. Rev. 2467P-08/07 1. Updated “Features” on page 2.
  • Page 21 Table 134 on page 323. 3. Updated “External Memory Interface” on page 4. Updated “Device Identification Register” on page 253. 5. Updated “Electrical Characteristics” on page 318. 6. Updated “ADC Characteristics” on page 325. 7. Updated “ATmega128 Typical Characteristics” on page 332. 2467RS–AVR–06/08...
  • Page 22 EEPROM during an SPM Page load. 10. Removed ADHSM completely. 11. Added section “EEPROM Write During Power-down Sleep Mode” on page 12. Updated drawings in “Packaging Information” on page Rev. 2467G-09/02 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. ATmega128 2467RS–AVR–06/08...
  • Page 23 (Boundary-Scan) 10. Updated Vil parameter in “DC Characteristics” on page 318. Rev. 2467E-04/02 1. Updated the Characterization Data in Section “ATmega128 Typical Characteristics” on page 332. 2. Updated the following tables: Table 19 on page Table 20 on page Table 68 on page...
  • Page 24 323, and Table 136 on page 328. 4. Corrected “Ordering Information” on page 5. Added some Characterization Data in Section “ATmega128 Typical Characteristics” on page 332. 6. Removed Alternative Algortihm for Leaving JTAG Programming Mode. See “Leaving Programming Mode” on page 315.
  • Page 25 ATmega128 7. Added Description on How to Access the Extended Fuse Byte Through JTAG Pro- gramming Mode. “Programming the Fuses” on page 317 “Reading the Fuses and Lock Bits” on page 317. 2467RS–AVR–06/08...
  • Page 26 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

This manual is also suitable for:

Atmega128l