Data Modes - Atmel AVR XMEGA D Series Manual

17.5

Data Modes

8210C–AVR–09/11
There are four combinations of SCK phase and polarity with respect to serial data. The SPI data
transfer formats are shown in
edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge
of a clock cycle.
Figure 17-2. SPI transfer modes.
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
Figure 17-2. Data bits are shifted out and latched in on opposite
MSB Bit 6 Bit 5 Bit 4
LSB Bit 1 Bit 2 Bit 3
MSB Bit 6 Bit 5
LSB Bit 1 Bit 2
Atmel AVR XMEGA D
Bit 3 Bit 2 Bit 1
Bit 4 Bit 5 Bit 6
Bit 4 Bit 3 Bit 2 Bit 1
Bit 3 Bit 4 Bit 5 Bit 6
LSB
MSB
LSB
MSB
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