Ericsson RBS 2106 Reference Manual page 414

Transmission Interface Handling G.703 2048 kbit/s
Table 181
Sub
multi
frame
1
2
CRC-4
c1, c2, c3, c4
A
E
Sa4, Sa5, Sa6, Sa7, Sa8
Downstream
Upstream
Linear Cascade Chain
412 (485)
Timeslot 0 and CRC-4 multiframe structure
Frame
number
1 2
0 c1 0
1 0 1
2 c2 0
3 0 1
4 c3 0
5 1 1
6 c4 0
7 0 1
8 cl 0
9 1 1
10 c2 0
11 1 1
12 c3 0
13 E 1
14 c4 0
15 E 1
Cyclic Redundancy Check (ITU-T G.704)
CRC-4 bits (see the section Layer 1
Termination 2048 kbit/s below)
Alarm bit (see the section Layer 1
Termination 2048 kbit/s below)
Error bit (see the section Layer 1
Termination 2048 kbit/s below)
Spare bits (see the section Layer 1
Termination 2048 kbit/s below)
The path for information from the BSC to
the MS, see Figure 142 on page 413
The path for information from the MS to
the BSC, see Figure 142 on page 413
A cascade of RBS:s according to Figure
142 on page 413
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— All Rights Reserved —
Bit 1 to 8 of timeslot 0
3 4 5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
0 1 1
A Sa4 Sa5
EN/LZT 720 0008
6 7 8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
0 1 1
Sa6 Sa7 Sa8
P2A
2001-11-28