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FUNCTIONAL DESCRIPTION
SYSFAIL*
< VMEbus System Fa i 1 ure Status>
A system fail ure, communi cated to thi s modu1 e vi a the VMEbus
SYSFAIL* signal, will set the SYSFAIL* flag
=
e.
If the SYSFIEN*
bit is set when a system failure occurs, the MVME135/136 interrupt
hand1 er wi 11 assert SF I RQ* to the processor.
VBER*
< VMEbus Bus Error>
VBER*
=
0, if a VMEbus reference made by this MVME135/136 caused a
bus error (i .e., only VMEbus bus errors made by this MVME135/136
when it is VMEbus master wi 11 be logged) .
VSBERR*
< VSBbus Bus Error>
VSBERR*
=
e, if a VSBbus reference made by this MVME135/136 caused
a bus error. VSBERR* will be asserted.
HMUBER*
< HMU Bus Error>
MMUBER*
=
0, when the bus error signal from the MMU device has been
asserted.
The MMU wi 11 assert BERR* and HAL T* to the MC68e2e
during Relinquish and Retry operations, in which it forces the
current logical bus master to terminate the current bus cycle.
release the logical bus, and retry the bus cycle when it is once
again logical bus master.
The concurrent assertion of HALT* and
BERR* by the MMU constitutes the Retry phase of the Re1 inquish and
Retry cycle.
The MMUBER* status bit will only indicate true MMU
cycle faults, not Relinquish and Retry cycle types.
LCLERR*
< Local Timeout Error>
LCLERR*, when low. indicates that a reference to a locally mapped
device caused a timeout bus error. This signal is also asserted if
an access attempt is made to local coprocessors such as the MC68881
or MC68851 that is not installed in the module.
4.15.2 Control Register Format And Functions
The following text describes the format and functions of the Control
Registers.
<CNT!>
Physical Address: $FFFBe00E
(Read/Write)
RC
=
None
007
006
005
004
003
002
001
000
, BRIROI',
WWP
I
PAREN'
I
VSBIEN
I
NA
NA
NA
NA
Access to this register will read the B port of the timer. Data bit
e7 should always be programmed as an input. Data bits e5 and e6 are
4-21
I
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