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I
FUNCTIONAL DESCRIPTION
128 microseconds, 256 microseconds, or infinite by setting bits 08
and 09 in the control register.
The timeout counter is started
when PAS* is asserted and is disabled when PAS* is negated. If the
counter times out before the PAS* signa 1 is nega ted the ERR* signa 1
is asserted and the BUSTIMEOUT* bit is set in the status register.
The times given are for ClK equal to 16.67 MHz.
ENTOl *
ENT00*
Timeout Period
1
1
Infinite
1
0
256 microseconds
0
1
128 microseconds
0
0
64 microseconds
Bit 10
ROBIN* < Round Robin Fairness Requester>
ROBIN* enables the fairness mode in the bus requester when
asserted.
Bus bandwidth is shared equally among VSBbus masters
that all have fairness mode.
When ROBIN* is negated, the bus
bandwidth is prioritized by a daisy-chain scheme where the modules
closest to the system controller will receive most of the available
bus bandwidth.
Bit 11
WRERROR* < Wr; te Error status Bit>
WRERROR* reports the fact that a write to a read only bus was
attempted.
Bit 12
BUSTIMEOUT* < VSBbus Timeout>
BUSTIMEOUT* reports the fact that a VSBbus timeout has occurred.
Bit 13
ASACKI:l* < Address And Si ze Status 0>
ASACK0* reports the status of the bus ASACK0* line
the 1 ast bus error.
Together wi th ASACKI *,
it
response and size of the sl ave modul e accessed.
foll owi ng chart.
ASACKl*
ASACK0*
Status
1
1
No Sl ave Response
1
0
8-Bit Slave Response
0
1
16-Bit Sl ave Response
0
0
32-Bit Slave Response
4-36
at the time of
i nd i cates the
Refer to the
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