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I
FUNCTIONAL DESCRIPTION
in the MPCSR (refer to section 4.16). SHPIEN*, when high, prevents
SIGHP from being set in the MPCSR. This restriction applys only to
Artwork Revisions A-C.
Artwork Revision E allows SIGHP to be set
independent of the state of SHPIEN*.
SLPIEN*
< Signal Low Priority Interrupt Enable>
SLPIEN*, when low, enables an interrupt to occur when SIGLP is set
in the MPCSR (refer to section 4.16). SLPIEN*, when high, prevents
SIGLP from being set in the
t~PCSR.
This restriction applys only to
Artwork Revisions A through C. Artwork Revision E allows SIGLP to
be set independent of the state of SLPIEN*.
LMIEN*
< Location Monitor Interrupt Enable>
LMIEN*, when low, enables an interrupt to occur from location
monitor zero, in the MPCSR (refer to section 4.16).
BRIRQO*
< Broadcast Interrupt Output>
BRIRQO*, when low, asserts VMEbus IRQ1*. This is not intended to
cause
a
VMEbus interrupt.
This bit is intended for use as a
broadcast mechanism that is compatible with the
MVME13~,
where
VMEbus IRQ1* is connected to bit
7
of Timer Port B and causes a
timer
interrupt.
The
MVME135/136
is
also
capable
of being
interrupted in this way.
Refer to the BRIRQI* description under
CNTl.
VSBIRQO*
< VSBbus Interrupt Output>
VSBIRQO*, when low, asserts VSBIRQ* low on VSBbus, allowing the
MVME135/136
to
generate
VSBbus
interrupts
for
diagnostics
applications.
<CNT4>
Physical Address: $FFFB003A
(Read/Write)
RC
=
1-------
007
006
005
004
003
002
001
000
IGLBRES-I
NA
NA
NA
NA
NA
NA
NA
GLBRES*
<Global Reset>
GLBRES*, when low, will cause
a
2~~
millisecond system reset. This
will happen whether the MVME135/136 is the system controller or
not. The data in this register is undefined when read.
4-24
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