Related Manuals for Xilinx M401
Summary of Contents for Xilinx M401
- Page 1 ML401/ML402/ML403 Evaluation Platform User Guide UG080 (v2.5) May 24, 2006 www.BDTIC.com/XILINX...
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Page 2: Revision History
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. - Page 3 Package Contents section. • Typographical corrections. 05/07/06 Updated USB interface chip criteria in Features section. 05/24/06 Updated USB interface chip criteria in Features section. Updated 18. ZBT Synchronous SRAM section. www.BDTIC.com/XILINX UG080 (v2.5) May 24, 2006 www.xilinx.com ML401/ML402/ML403 Evaluation Platform...
- Page 4 ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006...
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Page 5: Table Of Contents
20. Xilinx XC95144XL CPLD ........ - Page 6 Linear Flash + CPLD ............32 www.BDTIC.com/XILINX www.xilinx.com...
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Page 7: Preface: About This Guide
To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. Conventions This document uses the following conventions. An example illustrates each convention. -
Page 8: Online Document
Cross-reference link to a Figure 2-5 in the Virtex-II Red text location in another document Handbook. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... -
Page 9: Ml401/Ml402/Ml403 Evaluation Platform
ML402: 140 MHz / 24-bit video DAC ♦ ML403: 140 MHz / 15-bit video DAC • PS/2 mouse and keyboard connectors • System ACE™ CompactFlash configuration controller with Type I/II CompactFlash connector www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 10: Package Contents
10/100/1000 tri-speed Ethernet PHY transceiver • USB interface chip (Cypress CY7C67300) with host and peripheral ports • Xilinx XC95144XL CPLD to allow linear flash chips to be used for FPGA configuration • Xilinx XCF32P Platform Flash configuration storage device •... -
Page 11: Block Diagram
TPS54610 6A SWIFT to FPGA Core 5V Brick 3.3V TPS54310 3A SWIFT to FPGA I/O 1.8V TPS73118 150mA LDO to PROM UG080_01_050506 Figure 1: Virtex-4 ML40x Evaluation Platform Block Diagram www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 12: Detailed Description
(back). The numbered sections on the pages following the figures contain details on each feature. Note: The ML402 and ML403 boards might differ slightly from the board shown. UG080_02_101504 Figure 2: Detailed Description of Virtex-4 ML40x Evaluation Platform Components (Front) www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... - Page 13 The label on the CompactFlash (CF) card shipped with your board might differ slightly from the one shown. UG080_03_092004 Figure 3: Detailed Description of Virtex-4 ML40x Evaluation Platform Components (Back) www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006...
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Page 14: Virtex-4 Fpga
Detailed Description 1. Virtex-4 FPGA A Xilinx Virtex-4 FPGA is installed on the evaluation platform (the board): ♦ ML401: XC4VLX25-FF668-10 ♦ ML402: XC4VSX35-FF668-10 ♦ ML403: XC4VFX12-FF668-10 Configuration The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP modes. - Page 15 (pin 38 and 40). Yes, 49.9Ω resistors are installed. Yes, 49.9Ω resistors are installed. Not supported. a. Bank 9 and 10 are non-connected pins in the case of the ML403 board with XC4VFX12-FF668. www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006...
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Page 16: Ddr Sdram
This allows the FPGA to drive a precision clock to an external device such as a piece of test equipment. Table 3 summarizes the differential SMA clock pin connections. Table 3: Differential SMA Clock Connections Label Clock Name FPGA Pin SMA_DIFF_CLK_IN_N SMA_DIFF_CLK_IN_P SMA_DIFF_CLK_OUT_N SMA_DIFF_CLK_OUT_P www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... -
Page 17: Oscillator Sockets
Eight general purpose (active-High) DIP switches are connected to the user I/O pins of the FPGA. Table 5 summarizes these connections. Note: On the ML403 board, these DIP switches are not installed. Table 5: DIP Switches Connections (SW1) FPGA Pin www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 18: User And Error Leds (Active-High)
GPIO LED 1 Green GPIO LED 2 Green GPIO LED 3 Green DS205 Error 1 DS206* Error 2 Note: *On the ML403 board, the Error 2 LED is not installed. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... -
Page 19: User Push Buttons (Active-High)
This button is wired only to an FPGA I/O pin, so it can also be used as a general purpose button (see Table Table 8: CPU Reset Connections Reference Label/Definition FPGA Pin Designator SW10 FPGA CPU RESET www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 20: Expansion Headers
J5, Pin 56 J5, Pin 54 HDR2_44 HDR2_42 AF21 AF22 J5, Pin 60 J5, Pin 58 HDR2_32 HDR2_30 AF19 AF20 J5, Pin 64 J5, Pin 62 HDR2_40 HDR2_38 AF18 AE18 www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... - Page 21 J6, Pin 44 HDR1_54 J6, Pin 46 HDR1_56 J6, Pin 48 HDR1_46 J6, Pin 50 HDR1_20 AD25 J6, Pin 52 HDR1_14 AB22 J6, Pin 54 HDR1_48 J6, Pin 56 HDR1_44 www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006...
- Page 22 ML320, ML321, and ML323 boards, thereby allowing their daughter cards to be used with the ML40x evaluation platform. Table 11, page 23 summarizes the additional expansion I/O connections. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006...
- Page 23 GPIO LED 3 GPIO LED 3 J3, Pin 29 Not Connected J3, Pin 30 Not Connected J3, Pin 31 EXP_IIC_SCL Expansion IIC SCL J3, Pin 32 EXP_IIC_SDA Expansion IIC SDA www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006...
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Page 24: Stereo Ac97 Audio Codec
Care should be taken not to scratch or damage the surface of the LCD window. The protective layer of tape on the top of the screen should be left on for added protection of the screen's surface. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform... -
Page 25: Iic Bus With 4-Kb Eeprom
5V power jack, which also powers the rest of the board. Caution! Care must be taken to ensure that the power load of any attached PS/2 devices does not overload the AC adapter. www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 26: System Ace And Compactflash Connector
Detailed Description 17. System ACE and CompactFlash Connector The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE controller supports up to eight configuration images on a single CompactFlash card. -
Page 27: Linear Flash Chips
20. Xilinx XC95144XL CPLD A Xilinx XC95144XL CPLD is connected to the flash memory and the FPGA configuration signals. This CPLD connection supports applications where flash memory programs the FPGA. -
Page 28: Usb Controller With Host And Peripheral Ports
The JTAG configuration port for the board (J20) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products. Third-party configuration products might also be available. The JTAG chain can also be extended to an expansion board by setting jumper J26 accordingly. -
Page 29: Onboard Power Supplies
28. INIT LED The INIT LED lights upon power-up to indicate that the FPGA has successfully powered up and completed its internal power-on process. www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 30: Done Led
FPGA, make sure the FPGA configuration mode switches are set appropriately for the desired method of configuration. The PC4 connector allows JTAG download and debug of the board regardless of the setting of the configuration source selector switch. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006... -
Page 31: Configuration Options
CompactFlash card is present or whenever a CompactFlash card is inserted. Pressing the System ACE reset button also causes the System ACE controller to program the FPGA if a CompactFlash card is present. www.BDTIC.com/XILINX ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006... -
Page 32: Platform Flash Memory
The configuration source selector switch should be in the CPLD Flash setting if the use of CPLD + Platform Flash is desired. When set correctly, the CPLD programs the FPGA upon power-up or whenever the Prog button is pressed. www.BDTIC.com/XILINX www.xilinx.com ML401/ML402/ML403 Evaluation Platform UG080 (v2.5) May 24, 2006...