Xilinx M401 User Manual page 21

R
Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumper J16.
connections on this expansion I/O connector.
Table 10: Expansion I/O Single-Ended Connections (J6)
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ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
Table 10
Header Pin Label
J6, Pin 2 HDR1_28
J6, Pin 4 HDR1_42
J6, Pin 6 HDR1_36
J6, Pin 8 HDR1_2
J6, Pin 10 HDR1_52
J6, Pin 12 HDR1_32
J6, Pin 14 HDR1_26
J6, Pin 16 HDR1_12
J6, Pin 18 HDR1_50
J6, Pin 20 HDR1_38
J6, Pin 22 HDR1_40
J6, Pin 24 HDR1_22
J6, Pin 26 HDR1_10
J6, Pin 28 HDR1_60
J6, Pin 30 HDR1_24
J6, Pin 32 HDR1_4
J6, Pin 34 HDR1_30
J6, Pin 36 HDR1_6
J6, Pin 38 HDR1_34
J6, Pin 40 HDR1_18
J6, Pin 42 HDR1_16
J6, Pin 44 HDR1_54
J6, Pin 46 HDR1_56
J6, Pin 48 HDR1_46
J6, Pin 50 HDR1_20
J6, Pin 52 HDR1_14
J6, Pin 54 HDR1_48
J6, Pin 56 HDR1_44
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of these signals can be set to 2.5V or
CCIO
(spans onto next page) summarizes the single-ended
FPGA Pin
AA24
V20
AC25
AC24
W25
AB24
Y24
AB23
W26
Y26
Y25
AA26
AA23
AC21
AB26
AC23
AB25
AD23
AC26
AD26
AC22
V22
V21
W22
AD25
AB22
W21
W20
Detailed Description
21