Block Diagram - Xilinx M401 User Manual

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Block Diagram

Figure 1
FLASH
FLASH
GPIO
(Button/LED/DIP Switch)
Note: The DIP switch is
not available on the
ML403 board
100 MHz XTAL + User
SMA
(Differiential In/Out Clocks)
Dual PS/2
5V Brick
3A
Figure 1: Virtex-4 ML40x Evaluation Platform Block Diagram
www.BDTIC.com/XILINX
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
shows a block diagram of the ML40x evaluation platform (board).
CF PC
Sync
RAM
System ACE
Controller
32
Platform Flash
32
CPLD
32
Virtex-4
FPGA
I/O Expansion Header
5V to USB and PS/2
2.5V
TPS54310
3A SWIFT
1.2V
TPS54610
6A SWIFT
to FPGA Core
3.3V
TPS54310
3A SWIFT
to FPGA I/O
1.8V
TPS73118
150mA LDO
to PROM
www.xilinx.com
Host
USB
Peripheral
Controller
Peripheral
10/100/1000
Enet PHY
DDR SDRAM
DDR SDRAM
16 32
User IIC Bus
IIC EEPROM
1.25V
TPS51100
3A DDR LDO
to VTT
2.5V to DDR SDRAM
Introduction
RJ-45
Line Out/
Headphone
AC97
Audio CODEC
Mic In /
Line In
VGA
Video
Serial
RS-232 XCVR
16 X 32
Character LCD
UG080_01_050506
11