Ml401/Ml402/Ml403 Evaluation Platform; Introduction; Features - Xilinx M401 User Manual

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ML401/ML402/ML403 Evaluation Platform

Introduction

The ML401/ML402/ML403 evaluation platform enables designers to investigate and
experiment with features of the Virtex™-4 family of FPGAs. This user guide describes
features and operation of the ML401, ML402, and ML403 (ML40x) evaluation platforms.

Features

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www.BDTIC.com/XILINX
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
Virtex-4 FPGA:
♦
ML401: XC4VLX25-FF668-10
♦
ML402: XC4VSX35-FF668-10
♦
ML403: XC4VFX12-FF668-10
64-MB DDR SDRAM, 32-bit interface running up to 266-MHz data rate
One differential clock input pair and differential clock output pair with SMA
connectors
One 100-MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator
socket
General purpose DIP switches (ML401/ML402 platform), LEDs, and push buttons
Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs,
14 spare I/Os shared with buttons and LEDs, power, JTAG chain expansion
capability, and IIC bus expansion
Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, and
microphone-in (mono) jacks
RS-232 serial port
16-character x 2-line LCD display
One 4-Kb IIC EEPROM
VGA output:
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ML401: 50 MHz / 24-bit video DAC
♦
ML402: 140 MHz / 24-bit video DAC
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ML403: 140 MHz / 15-bit video DAC
PS/2 mouse and keyboard connectors
System ACE™ CompactFlash configuration controller with Type I/II CompactFlash
connector
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