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19. Linear Flash Chips
Two 32-Mb linear flash devices (Micron MT28F320J3RG-11 ET) are installed on the board
for a total of 8 MB of flash memory. These flash memory chips are Intel StrataFlash
compatible. This memory provides non-volatile storage of data, software, or bitstreams.
Each flash chip is 16 bits wide and together forms a 32-bit data bus that is shared with
SRAM. In conjunction with a CPLD, the flash memory can also be used to program the
FPGA.
Note:
is designed to be asserted at power-on or upon system reset.
20. Xilinx XC95144XL CPLD
A Xilinx XC95144XL CPLD is connected to the flash memory and the FPGA configuration
signals. This CPLD connection supports applications where flash memory programs the
FPGA. The CPLD is programmed from the main JTAG chain of the board. The CPLD is
wired so that it can support master or slave configuration in serial or parallel (SelectMAP)
modes. For FPGA configuration via the CPLD and flash, the configuration selector switch
(SW12) must be set to the CPLD Flash position. See the
section for more information.
21. 10/100/1000 Tri-Speed Ethernet PHY
The ML40x evaluation platform contains a Marvell Alaska PHY device (88E1111) operating
at 10/100/1000 Mb/s. The board supports MII, GMII, and RGMII interface modes with the
FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 connector with built-in
magnetics. A 25-MHz crystal supplies the clock signal to the PHY. The PHY is configured
to default at power-on or reset to the following settings (See
be overwritten via software.
Table 14: Board Connections for PHY Configuration Pins
Connection on
Config Pin
Board
CONFIG0
Ground
CONFIG1
Ground
CONFIG2
V
2.5V
CC
CONFIG3
V
2.5V
CC
CONFIG4
V
2.5V
CC
CONFIG5
V
2.5V
CC
CONFIG6
LED_RX
www.BDTIC.com/XILINX
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
The reset for the AC97 Codec is shared with the reset signal for the flash memory chips and
Bit[2] Definition and
Value
PHYADR[2] = 0
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MODE[2] = 1
DIS_FC = 1
SEL_BDT = 0
www.xilinx.com
"Configuration Options," page 31
Bit[1] Definition and
Value
PHYADR[1] = 0
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MODE[1] = 1
DIS_SLEEP = 1
INT_POL = 1
Detailed Description
Table
14). These settings may
Bit[0] Definition and Value
PHYADR[0] = 0
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MODE[0] = 1
HWCFG_MODE[3] = 1
75/50Ω = 0
27
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