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8.1
A-B Connector Signal Descriptions
Table 10
Intel
®
High Definition Audio Link Signals Descriptions
Signal
Pin #
AC/HDA_RST#
A30
AC/HDA_SYNC
A29
AC/HDA_BITCLK
A32
AC/HDA_SDOUT
A33
AC/HDA_SDIN[1:0] B29-B30 Intel
Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user's guide.
Table 11
Gigabit Ethernet Signal Descriptions
Gigabit
Pin # Description
Ethernet
GBE0_MDI0+
A13
GBE0_MDI0-
A12
GBE0_MDI1+
A10
GBE0_MDI1-
A9
GBE0_MDI2+
A7
GBE0_MDI2-
A6
GBE0_MDI3+
A3
GBE0_MDI3-
A2
GBE0_ACT#
B2
GBE0_LINK#
A8
GBE0_LINK100#
A4
GBE0_LINK1000#
A5
Copyright © 2017 congatec AG
Description
Intel
®
High Definition Audio Reset: This signal is the master hardware reset to
external codec(s).
Intel
®
High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync
to the codec(s). It is also used to encode the stream number.
Intel
High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial
®
data clock generated by the Intel
®
High Definition Audio controller.
Intel
High Definition Audio Serial Data Out: This signal is the serial TDM data
®
output to the codec(s). This serial output is double-pumped for a bit rate of 48
Mbps for Intel
High Definition Audio.
®
High Definition Audio Serial Data In [0]: These signals are serial TDM
®
data inputs from the three codecs. The serial input is single-pumped for a bit
rate of 24 Mbps for Intel
High Definition Audio.
®
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate
in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:
1000
MDI[0]+/-
B1_DA+/-
MDI[1]+/-
B1_DB+/-
MDI[2]+/-
B1_DC+/-
MDI[3]+/-
B1_DD+/-
Gigabit Ethernet Controller 0 activity indicator, active low.
Gigabit Ethernet Controller 0 link indicator, active low.
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.
I/O
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
I 3.3VSB
100
10
TX+/-
TX+/-
RX+/-
RX+/-
TCKLm10
PU/PD Comment
AC'97 codecs are not supported.
AC'97 codecs are not supported.
AC'97 codecs are not supported.
PU 1K
AC'97 codecs are not supported.
3.3VSB
AC/HDA_SDOUT is a boot strap signal
(see note below)
Pin B28 (HDA_SDIN2) is not connected.
I/O
PU/PD Comment
I/O
Twisted pair
Analog
signals for
external
transformer.
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
43/71
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