Releasing Halt Mode By Reset Input - NEC PD789860 User Manual

(c) Releasing by RESET input
When HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as the ordinary reset operation, and program execution starts.
RESET
signal
Operating
mode
Clock
Note In the
In the
In the
Remarks 1. f
2. f
Releasing Source
Maskable interrupt request
Non-maskable interrupt request
of watchdog timer
RESET input
×: don't care
152
CHAPTER 15 STANDBY FUNCTION
Figure 15-3. Releasing HALT Mode by RESET Input
HALT
instruction
HALT mode
Oscillation
µ
15 17
PD789860, 2 /f or 2 /f can be selected by using the mask option.
X X
µ
15
PD78E9860A, 2 /f : 6.55 ms (@f
X
µ
PD789861 and 78E9861A, 2
: System clock oscillation frequency (ceramic/crystal oscillation)
X
: System clock oscillation frequency (RC oscillation)
CC
Table 15-2. Operation After Releasing HALT Mode
MK×× IE
0 0
0 1
×
1
− ×
− −
User's Manual U14826EJ5V0UD
Note
Wait
Oscillation
stabilization
Reset
wait status
period
Oscillation
stop Oscillation
= 5.0 MHz operation)
X
µ
7
/f : 128 s (@f = 1.0 MHz operation)
CC CC
Operation
Executes next address instruction.
Executes interrupt servicing.
Retains HALT mode.
Executes interrupt servicing.
Reset processing
Operating
mode