Chapter 5 Eeprom (Data Memory); Memory Space; Eeprom Configuration; Eeprom Control Register - NEC PD789860 User Manual

5.1 Memory Space

Besides internal high-speed RAM, the
PROM (EEPROM) on-chip as data memory.
Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. In addition, unlike
EPROM, its contents can be electrically erased without using ultraviolet rays.

5.2 EEPROM Configuration

EEPROM consists of the EEPROM itself and a control section.
The control section consists of EEPROM write control register 10 (EEWC10) which controls EEPROM writing and
a part that detects the termination of writing and generates an interrupt request signal (INTEE0).
Data latch
EEPROM
Address
latch
(32 × 8 bits)

5.3 EEPROM Control Register

EEPROM is controlled by EEPROM write control register 10 (EEWC10).
EEWC10 is the register that sets the EEPROM count clock selection, and EEPROM write control.
EEWC10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 08H.
Figure 5-2 shows the format of EEPROM write control register 10. Tables 5-1 and 5-2 show EEPROM write times.
58

CHAPTER 5 EEPROM (DATA MEMORY)

µ
PD789860, 789861 Subseries have 32 × 8 bits of electrically erasable
Figure 5-1. EEPROM Block Diagram
Internal bus
EWCS102 EWCS101 EWCS100
EEPROM timer
Read/write
controller
User's Manual U14826EJ5V0UD
EEPROM write control register 10 (EEWC10)
EWST10 EWE10
ERE10
5
f /2
X
(µPD789860 Subseries)
Prescaler
5
f /2
CC
8-bit timer 40 output
INTEE0
7
to f /2
X
(µPD789861 Subseries)