Watchdog Timer Operation; Operation As Watchdog Timer - NEC PD789860 User Manual

10.4 Watchdog Timer Operation

10.4.1 Operation as watchdog timer

The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 0
to 2 (TCL20 to TCL22) of the timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the
watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after the
watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN
is not set to 1, and the inadvertent program loop detection time is exceeded, a system reset signal or a non-maskable
interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the watchdog timer before executing the STOP instruction.
Caution The actual inadvertent program loop detection time may be up to 0.8% shorter than the set time.
Table 10-4. Inadvertent Program Loop Detection Time of Watchdog Timer
TCL22 TCL21
0
0
1
1
Other than above
Remarks 1. f
2. f
122
CHAPTER 10 WATCHDOG TIMER
TCL20 At f = 5.0 MHz Operation
X
µ
11
0 0 2 /f (410 s)
X
13
1 0 2 /f (1.64 ms)
X
15
0 0 2 /f (6.55 ms)
X
17
1 0 2 /f (26.2 ms)
X
Setting prohibited
: System clock oscillation frequency (ceramic/crystal oscillation)
X
: System clock oscillation frequency (RC oscillation)
CC
User's Manual U14826EJ5V0UD
At f = 1.0 MHz Operation
CC
11
2 /f (2.05 ms)
CC
13
2 /f (8.19 ms)
CC
15
2 /f (32.8 ms)
CC
17
2 /f (131.1 ms)
CC