Stop Mode - NEC PD789860 User Manual

15.2.2 STOP mode

(1) Setting and operation status of STOP mode
STOP mode is set by executing the STOP instruction.
Caution Because standby mode can be released by an interrupt request signal, standby mode is
released as soon as it is set if there is an interrupt source whose interrupt request flag is
set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set
immediately after the STOP instruction has been executed, the oscillation stabilization time
elapses, and then the operation mode is set.
The operation statuses in STOP mode are shown in the following table.
Item
System clock
CPU
EEPROM
Port (output latch)
8-bit timer TM30
TM40
Watchdog timer
Power-on-clear POC
circuit
LVI
Bit sequential buffer
Key return circuit
Notes 1. Operation enabled only when cascade connected with TM40 (external clock selected for count clock)
2. Operation enabled only when external clock is selected for count clock
3. If a POC switching circuit is selected by the mask option and the POC circuit is set to operation enabled
by software or if POC circuit normally operating is selected by the mask option (see CHAPTER 18
MASK OPTIONS regarding mask options).
4. Operation enabled only when external clock is selected for TM40 count clock and INTTM40 occurs
CHAPTER 15 STANDBY FUNCTION
Table 15-3. Operation Statuses in STOP Mode
System clock oscillation stopped
Clock supply to CPU stopped
Operation stopped
Operation stopped
Remains in the state existing before STOP mode has been set
Note 1
Operation enabled
Note 2
Operation enabled
Operation stopped
Note 3
Operation enabled
Operation stopped
Note 4
Operation enabled
Operation enabled
User's Manual U14826EJ5V0UD
STOP Mode Operation Status
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