Lvi Circuit Operation Timing - NEC PD789860 User Manual

(c) Processing to enable LVI interrupt again after LVI interrupt servicing
SET1 LVIMK1;
CLR1 LVION1;
SET1 LVION1;
CLR1 LVIMK1;
EI
Figure 11-9 shows the LVI circuit operation timing.
Power supply voltage (V )
DD
Detection voltage (V )
LVI
1.8 V
LVION1
IE
INTLVI1
LVIIF1
LVIMK1
Caution The low-voltage detection interrupt request flag (LVIIF1) is set at the rising edge of the LVI
circuit comparator output signal (INTLVI1). Therefore, the power supply voltage (V
lower than the detection voltage (V
INTLVI1 generation, LVIIF1 is not set. After low-voltage detection, when set as V
then V < V
DD LVI
CHAPTER 11 POWER-ON-CLEAR CIRCUITS
LVI interrupt disabled
LVI operation disabled
LVI operation enabled
LVI interrupt enabled
Figure 11-9. LVI Circuit Operation Timing
2 ms
) during LVI operation, and if that state continues after
LVI
again, LVIIF1 is set.
User's Manual U14826EJ5V0UD
Vectored interrupt
Vectored interrupt does not occur
) becomes
DD
> V and
DD LVI
131