Figure 4-4. Data Memory Addressing (
F F F F H
Special function registers (SFR)
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Reserved
F 8 2 0 H
F 8 1 F H
EEPROM
(data memory)
32 × 8 bits
F 8 0 0 H
F 7 F F H
Reserved
1 0 0 0 H
0 F F F H
EEPROM
(program memory)
4,096 × 8 bits
0 0 0 0 H
CHAPTER 4 CPU ARCHITECTURE
µ
PD78E9860A, 78E9861A)
SFR addressing
User's Manual U14826EJ5V0UD
Short direct addressing
Direct addressing
Register indirect addressing
Based addressing
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