NEC PD789860 User Manual page 175

Mnemonic Operand
CMP A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
ADDW AX, #word
SUBW AX, #word
CMPW AX, #word
INC r
saddr
DEC r
saddr
INCW rp
DECW rp
ROR A, 1
ROL A, 1
RORC A, 1
ROLC A, 1
SET1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Remark One instruction clock cycle is one CPU clock cycle (f
register (PCC).
CHAPTER 19 INSTRUCTION SET OVERVIEW
Bytes Clocks
A − byte
2 4
(saddr) − byte
3 6
A − r
2 4
A − (saddr)
2 4
A − (addr16)
3 8
A − (HL)
1 6
A − (HL + byte)
2 6
AX, CY ← AX + word
3 6
AX, CY ← AX − word
3 6
AX − word
3 6
r ← r + 1
2 4
(saddr) ← (saddr) + 1
2 4
r ← r − 1
2 4
(saddr) ← (saddr) − 1
2 4
rp ← rp + 1
1 4
rp ← rp − 1
1 4
1 2 (CY, A
1 2 (CY, A
(CY ← A
1 2
(CY ← A
1 2
(saddr.bit) ← 1
3 6
sfr.bit ← 1
3 6
A.bit ← 1
2 4
PSW.bit ← 1
3 6
(HL).bit ← 1
2 10
(saddr.bit) ← 0
3 6
sfr.bit ← 0
3 6
A.bit ← 0
2 4
PSW.bit ← 0
3 6
(HL).bit ← 0
2 10
CY ← 1
1 2
CY ← 0
1 2
CY ← CY
1 2
User's Manual U14826EJ5V0UD
Operation
← A ← A ) × 1
, A
7 0 m−1 m
← A ← A ) × 1
, A
0 7 m+1 m
← CY, A ← A ) × 1
, A
0 7 m−1 m
← CY, A ← A ) × 1
, A
7 0 m+1 m
) selected by the processor clock control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
×
×
×
×
× × ×
× × ×
1
0
×
175