Format Of Low-Voltage Detection Register 1 - NEC PD789860 User Manual

(2) Low-voltage detection register 1 (LVIF1)
LVIF1 controls the operation of the LVI circuit.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Symbol <7> 6
LVIF1 LVION1 0
LVION1
0 LVI disabled
1 LVI enabled
LVF10
0 Power supply voltage (V
1 V < V
DD LVI
Note Bit 0 is read only.
(3) Low-voltage detection level selection register 1 (LVIS1)
LVIS1 selects the level of the detection voltage (V
This register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 11-5. Format of Low-Voltage Detection Level Selection Register 1
Symbol 7 6
LVIS1 0 0
LVS12 LVS11
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note See CHAPTER 20 ELECTRICAL SPECIFICATIONS for detection voltage specifications.
Caution When changing the detection voltage level (V
ms is required in order for the LVI output to stabilize. Do not, therefore, set the LVI circuit
to operation-enable until the operation has stabilized.
CHAPTER 11 POWER-ON-CLEAR CIRCUITS
Figure 11-4. Format of Low-Voltage Detection Register 1
5 4 3
0 0 0
) > LVI detection voltage (V
DD
5 4 3
0 0 0
LVS10
0 V
LVI0
1 V
LVI1
0 V
LVI2
1 V
LVI3
0 V
LVI4
1 V
LVI5
0 V
LVI6
1 V
LVI7
User's Manual U14826EJ5V0UD
2 1 <0>
0 0 LVF10
LVI operation enable flag
LVI output detection flag
) or operation disabled
LVI
).
LVI
<2> <1> <0>
LVS12 LVS11 LVS10
Selection of detection voltage (V
), an operation stabilization time of about 2
LVI
Address After reset R/W
Note
FFDEH 00H R/W
Address After reset R/W
FFDFH 00H R/W
Note
) level
LVI
127