Electrical characteristics
6.3.16
Communications interfaces
2
I
C interface characteristics
The device I
protocol with the following restrictions: SDA and SCL are not "true" open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and V
disabled, but is still present.
2
The I
C characteristics are described in
characteristics
Symbol
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
t
su(STO)
t
w(STO:STA)
C
b
t
SP
1. Guaranteed by design.
2. f
must be at least 2 MHz to achieve standard mode I
PCLK1
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above t
94/134
2
C interface meets the requirements of the standard I
for more details on the input/output ction characteristics (SDA and SCL) .
Table 47. I
Parameter
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
Pulse width of spikes that
are suppressed by the
analog filter
DocID025433 Rev 8
STM32L151xE STM32L152xE
Table
47. Refer also to
2
C characteristics
Standard mode
2
(1)(2)
I
C
Min
Max
4.7
-
4.0
-
250
-
(3)
-
3450
-
1000
-
300
4.0
-
4.7
-
4.0
-
4.7
-
-
400
(4)
0
50
C frequencies. It must be at least 4 MHz to
²
SP(max)
2
C communication
is
DD
Section 6.3.13: I/O port
2
(1)(2)
Fast mode I
C
Min
Max
1.3
-
0.6
-
100
-
(3)
-
900
-
300
-
300
0.6
-
0.6
-
0.6
-
1.3
-
-
400
(4)
0
50
.
Unit
µs
ns
µs
μs
μs
pF
ns
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