STMicroelectronics STM32L151RE Manual page 133

STM32L151xE STM32L152xE
Date
10-Feb-2015
27-Apr-2015
09-Feb-2016
Table 73. Document revision history (continued)
Revision
Updated Section : In order to meet environmental requirements, ST
offers these devices in different grades of ECOPACK® packages,
depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
6
www.st.com. ECOPACK® is an ST trademark.
device marking.
Updated Figure 8: Memory
Updated Section 7: Package information
and paragraph heading level.
Updated Section 7.1: LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package information
text for device orientation versus pin1 identifier.
Updated Section 7.2: LQFP100, 14 x 14 mm, 100-pin low-profile quad
flat package information
note for device orientation versus pin 1 identifier.
Updated Section 7: Package information
marking adding text in for device orientation versus pin 1 or ball A1
identifier.
7
Added Figure 44: WLCSP104, 0.4 mm pitch wafer level chip scale
package recommended footprint
pitch recommended PCB design
Updated Table 8: STM32L151xE and STM32L152xE pin definitions
ADC inputs.
Updated Table 16: Embedded internal reference voltage
coefficient at 100ppm/°C.
and table footnote 3: "guaranteed by design" changed by "guaranteed
by characterization results".
Updated Table 63: Comparator 2 characteristics
threshold voltage temperature coefficient at 100ppm/°C.
Updated cover page putting eight SPIs in the peripheral
communication interface list.
Updated Table 2: Ultra-low-power STM32L151xE and STM32L152xE
device features and peripheral counts
Updated Table 39: ESD absolute maximum ratings
class C3 and C4 depending of the package.
8
Updated all the notes, removing 'not tested in production'.
Updated Table 10: Voltage characteristics
pin.
Updated Table 5: Functionalities depending on the working mode (from
Run/active down to standby)
Standby mode.
DocID025433 Rev 8
Changes
with new package
map.
structure: Paragraph titles
removing gate mark in Figure 33
removing gate mark in Figure 36
for all other package device
and Table 70: WLCSP104, 0.4 mm
rules.
SPI and I2S lines.
adding note about V
LSI and LSE functionalities putting "Y" in
Revision History
and adding
and adding
temperature
new maximum
CDM class II by
REF-
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