Table 70. Wlcsp104, 0.4 Mm Pitch Recommended Pcb Design Rules; Figure 45. Wlcsp104, 0.4 Mm Pitch Wafer Level Chip Scale Package Top View Example - STMicroelectronics STM32L151RE Manual

Package information
Dimension
Pitch
Dpad
Dsm
PCB pad design
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.

Figure 45. WLCSP104, 0.4 mm pitch wafer level chip scale package top view example

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Table 70. WLCSP104, 0.4 mm pitch recommended PCB design rules

DocID025433 Rev 8
STM32L151xE STM32L152xE
Recommended values
0.4
260 µm max. (circular)
220 µm recommended
300 µm min. (for 260 µm diameter pad)
Non-solder mask defined via underbump allowed.