Electrical characteristics
Figure 28. Maximum dynamic current consumption on V
ADC clock
I
ref+
700µA
300µA
Ts
Ts
(cycles)
(µs)
2.4 V < V
4
0.25
9
0.5625
16
1
24
1.5
48
3
96
6
192
12
384
24
1. Guaranteed by design, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in The 10 nF capacitors should be
ceramic (good quality). They should be placed as close as possible to the chip.
96/129
Sampling (n cycles)
Table 56. R
AIN
Multiplexed channels
< 3.6 V 1.8 V < V
DDA
Not allowed
Not allowed
0.8
Not allowed
2.0
3.0
6.8
15.0
32.0
50.0
DocID17659 Rev 10
STM32L151x6/8/B, STM32L152x6/8/B
conversion
Conversion (12 cycles)
max for f
= 16 MHz
ADC
R
max (kOhm)
AIN
< 2.4 V 2.4 V < V
DDA
0.8
1.8
4.0
10.0
25.0
50.0
supply pin during ADC
REF+
(1)
Direct channels
< 3.3 V
1.8 V < V
DDA
0.7
Not allowed
2.0
4.0
6.0
15.0
10.0
30.0
20.0
50.0
40.0
50.0
50.0
< 2.4 V
DDA
1.0
3.0
4.5
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