Figure 22. Spi Timing Diagram - Slave Mode And Cpha = 0; Figure 23. Spi Timing Diagram - Slave Mode And Cpha = 1 - STMicroelectronics STM32L151CB Manual

STM32L151x6/8/B, STM32L152x6/8/B
NSS input
CPHA= 0
CPOL=0
t w(SCKH)
CPHA= 0
t w(SCKL)
CPOL=1
t a(SO)
MISO
OUT P UT
t su(SI)
MOSI
I NPUT
NSS input
t SU(NSS)
CPHA=1
CPOL=0
t w(SCKH)
CPHA=1
t w(SCKL)
CPOL=1
t a(SO)
MISO
OUT P UT
MOSI
I NPUT
1. Measurement points are done at CMOS levels: 0.3V

Figure 22. SPI timing diagram - slave mode and CPHA = 0

t c(SCK)
t SU(NSS)
t v(SO)
MS B O UT
M SB IN
t h(SI)

Figure 23. SPI timing diagram - slave mode and CPHA = 1

t v(SO)
MS B O UT
t su(SI)
t h(SI)
M SB IN
DocID17659 Rev 10
t h(SO)
BI T6 OUT
B I T1 IN
t c(SCK)
t h(SO)
BI T6 OUT
B I T1 IN
and 0.7V
DD DD.
Electrical characteristics
t h(NSS)
t r(SCK)
t dis(SO)
t f(SCK)
LSB OUT
LSB IN
(1)
t h(NSS)
t r(SCK)
t dis(SO)
t f(SCK)
LSB OUT
LSB IN
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