GE L60 Instruction Manual page 606

OVERVIEW CHAPTER 9: THEORY OF OPERATION
This is undesirable because it introduces an error in the phase comparison. There is no way to eliminate this phase delay
but there is a way to compensate for it. This compensation is accomplished by the phase delay timer in the comparer input
circuit.
9.1.7.2 Phase delay adjustment
The phase delay adjustment is a timer that is set with a pickup and a drop-out delay that are equal to each other so that it
introduces a phase delay without affecting the symmetry of the input signal. Its output is the same shape as that of the
squaring amplifier but delayed in time by the setting. This time delay setting is made in the field to be just equal to the sum
of the three delays (symmetry adjustment, propagation, and receiver) discussed earlier. Thus, with this arrangement in the
scheme of the previous figure, an external fault produces an output from the symmetry adjustment logic exactly in phase
and symmetrical with the output of the phase delay logic. This is necessary for proper blocking. For internal faults, the
output from the phase delay timer is symmetrical with, but 180 degrees out of phase with the receiver output. This is
necessary for tripping. Note that any errors in these adjustments can reduce the tripping margins for internal faults and/or
reduce the blocking margins during external faults.
Note that the setting of the phase delay timer depends on the channel operating time, and that the total tripping time of
the scheme is affected by this timer setting. Thus, the tripping speed of the scheme depends to that degree on the channel
operating time.
9.1.7.3 Transient blocking
Transient blocking is a feature that is included in all phase comparison schemes. It adds to the security of the scheme
during and immediately after the clearing of external faults. The following figure is a representation of Figure 1-15 except
with the transient blocking logic added. This consists of AND3, AND4, and the (15-99)/(15-99) transient blocking timer.
Figure 9-16: Blocking scheme with transient blocking logic
The logic of the transient blocking scheme is such that if a fault is detected (indicated by the operation of FDH) but no trip
takes place (as indicated by no output from the trip integrator timer), then AND3 produces an output to the transient
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blocking timer (15-99)/(15-99). If this condition persists long enough for the transient blocking timer to produce an output,
tripping is blocked via the NOT input to AND4. This blocking of a trip output persists for the drop-out time setting of the
transient blocking timer after the AND3 output disappears as a result of FDH resetting or the trip integrator producing an
output.
9-24 L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUAL