Board-Level Bmp Diagnostics - GE LOGIQ 9 Technical Manual

GE M S
EDICAL YSTEMS
D 2294854-100, R
IRECTION
7-7-4-2

Board-Level BMP Diagnostics

Probe
• All Board-Level BMP Diags: Tests vector generation and Scan Bus emulation on the BMP. This
configuration further tests the SCB's Clock Generation and PCI bridge, but does not rely on the
Scan Sequencer or Image Port functions of the SCB.
Not tested on the BMP, with this diagnostic, are its abilities to receive and correctly process the
TxSync, RxSync, IQ data, and Scan Bus inputs, as well as its ability to drive the BM output data to
the SCB. These functions will be tested with a system-level diagnostic.
The following subsections outline the Board-Level BMP Diagnostics.
• BMP PCI Interface Diag: Tests the Host's ability to communicate with the BMP via the PCI bus.
NOTE: A preferred test strategy for the PCI 9054 Interface is detailed in
• BMP Memory Diag: Tests all of the on-board memory, including registers.
NOTE: Guidelines in
• BMP Signal Path Diag: Tests the entire BMP signal path with a series of input vectors and scan
parameters (both from the on-board test vector generator), whose results are each read out of a
FIFO in the BM Output section of the board.
The following BMP functions are tested:
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-
-
-
-
The BM data read from the Output block's FIFO may then be compared to gold file data for
verification and fault isolation.
7-24
PROPRIETARY TO GE
3
EVISION
IIC
RF RF
XDIF/RF
PCI
Host
Figure 7-22 Board-Level BMP Block Diagram
Section 7-9 will enumerate the memory locations.
Synthetic Aperture
Axial Interpolator
Detector
Vector Compounder
Rate Converter
Section 7-7 - Acquisition Diagnostics
IQ RxSYNC
TD's EQ
Scan Control Board
- Dynamic Range Compression
- Edge Enhance
- Splicer
- BM Output, with exception of the output signal drivers
- Memory Banking
LOGIQ™ 9 P
ROPRIETARY
IQ,
BM
BMP
Section 7-8.
M
ANUAL