Eaton EMR-4000 Installation, Operation And Maintenance Manual page 823

Name
IEC61850.VirtInp25
IEC61850.VirtInp26
IEC61850.VirtInp27
IEC61850.VirtInp28
IEC61850.VirtInp29
IEC61850.VirtInp30
IEC61850.VirtInp31
IEC61850.VirtInp32
Logic.LE1.Gate Out
Logic.LE1.Timer Out
Logic.LE1.Out
Logic.LE1.Out inverted
Logic.LE2.Gate Out
Logic.LE2.Timer Out
Logic.LE2.Out
Logic.LE2.Out inverted
Logic.LE3.Gate Out
Logic.LE3.Timer Out
Logic.LE3.Out
Logic.LE3.Out inverted
Logic.LE4.Gate Out
Logic.LE4.Timer Out
Logic.LE4.Out
Logic.LE4.Out inverted
Logic.LE5.Gate Out
Logic.LE5.Timer Out
Logic.LE5.Out
Logic.LE5.Out inverted
Logic.LE6.Gate Out
Logic.LE6.Timer Out
Logic.LE6.Out
Logic.LE6.Out inverted
Logic.LE7.Gate Out
Logic.LE7.Timer Out
Logic.LE7.Out
Logic.LE7.Out inverted
Logic.LE8.Gate Out
Description
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Virtual Input (IEC61850 GGIO Ind)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
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EMR-4000 IM02602009E
823