Eaton EMR-4000 Installation, Operation And Maintenance Manual page 342

Signals that can be used for PSS
Name
-.-
DI-8P X1.DI 1
DI-8P X1.DI 2
DI-8P X1.DI 3
DI-8P X1.DI 4
DI-8P X1.DI 5
DI-8P X1.DI 6
DI-8P X1.DI 7
DI-8P X1.DI 8
Logic.LE1.Gate Out
Logic.LE1.Timer Out
Logic.LE1.Out
Logic.LE1.Out inverted
Logic.LE2.Gate Out
Logic.LE2.Timer Out
Logic.LE2.Out
Logic.LE2.Out inverted
Logic.LE3.Gate Out
Logic.LE3.Timer Out
Logic.LE3.Out
Logic.LE3.Out inverted
Logic.LE4.Gate Out
Logic.LE4.Timer Out
Logic.LE4.Out
Logic.LE4.Out inverted
Logic.LE5.Gate Out
Logic.LE5.Timer Out
Logic.LE5.Out
Logic.LE5.Out inverted
Logic.LE6.Gate Out
Logic.LE6.Timer Out
Logic.LE6.Out
Logic.LE6.Out inverted
Logic.LE7.Gate Out
Logic.LE7.Timer Out
Description
No assignment
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Digital Input
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
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EMR-4000 IM02602009E
342