Packet Forwarding Engine Clock Generators (Pcgs); Figure 6: Fpc1 And Fpc2 - Juniper Internet Router M160 Hardware Manual

M160 Internet Router Hardware Guide

Figure 6: FPC1 and FPC2

FPC 1
Ejector lever
Offline buttons
(on FPC)
Ejector lever

Packet Forwarding Engine Clock Generators (PCGs)

The router has two Packet Forwarding Engine Clock Generators (PCGs) installed
in the slots at the rear of the chassis that are labeled
in Figure 3. The PCGs generate a 125-MHz clock signal used to gate packet
processing. During startup, the active Routing Engine determines which PCG is
master and which is backup, and the MCS relays the decision to the PCGs and to
the modules and ASICs in the Packet Forwarding Engine that use the clock signal.
The modules and ASICs then use only the signal from the master source.
PCGs are hot-pluggable, as described in Field-Replaceable Units (FRUs) on page 4.
Removal or failure of the backup PCG does not affect router function. When the
master PCG fails or is removed from the chassis, however, the Packet Forwarding
Engine resets so that the components start using the signal from the other PCG
(which becomes the master). Packet forwarding halts while there is no clock signal,
because the Packet Forwarding Engine does not accept incoming packets. For
PCG replacement instructions, see "Replacing a PCG" on page 176.
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Packet Forwarding Engine
FPC 2
Ejector lever
Offline buttons
(on PICs)
Ejector lever
PCG 0
and , as shown
PCG 1