Supplemental Characteristics (Logic Analyzer) - HP 1660CS-Series User Manual

Specifications

Supplemental characteristics (logic analyzer)

Supplemental characteristics (logic analyzer)
Probes
Input resistance
Input capacitance
Minimum voltage swing
Threshold range
State analysis
State/Clock qualifiers
*
Time tag resolution
Maximum time count
between states
Maximum state tag count
* Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to a state or
timing machine, time or state tags halve the memory depth.
Timing analysis
Sample period accuracy
Channel-to-channel skew
Time interval accuracy
Triggering
Sequence speed
State sequence levels
Timing sequence levels
Maximum occurrence counter
value
Pattern recognizers
Maximum pattern width
Range recognizers
11–6
100 kΩ, ± 2%
~ 8 pF
500 mV, peak-to-peak
± 6.0 V, adjustable in 50-mV increments, CAT I
1660/61C - 6; 1662CS - 4; 1663CS - 2
8 ns or 0.1%, whichever is greater
34 seconds
* 9
4.29 x 10
0.01 % of sample period
2 ns, typical
± [sample period + channel-to-channel skew
+(0.01%)(time reading)]
125 MHz, maximum
12
10
1,048,575
10
136 channels in HP 1660CS, 102 channels in
HP 1661CS, 68 channels in HP 1662CS,
34 channels in HP 1663CS
2