Supplemental Characteristics (Logic Analyzer) - HP 1660CP Series User Manual

Logic levels
Data inputs
Clock outputs
Clock input
Internal clock period
External clock period (user supplied)
External duty cycle
Maximum number of "IF condition"
blocks at 50 MHz
Maximum number for different Macros
Maximum number of lines in a Macro
Maximum number of Macro invocations
Maximum number of repeat loop
invocations
Maximum number of Wait event patterns

Supplemental characteristics (logic analyzer)

Probes
Input resistance
Input capacitance
Minimum voltage swing
Threshold range
Supplemental characteristics (logic analyzer)
TTL, 3-state, TTL/3.3v,
3-state TTL/CMOS, ECL terminated,
ECL Unterminated, and differential
ECL (without POD)
3-bit pattern - level sensing (clock pod)
Synchronized to output data
DC to 200 MHz
Programmable from 5 ns to 250 us
in a 1, 2, 2.5, 4, 5, 8 sequence
DC to 200 MHz
2 ns minimum high time
1
100
1024
1000
1000
4
100 kΩ, ± 2%
~ 8 pF
500 mV, peak-to-peak
± 6.0 V, adjustable in 50-mV increments, CAT I
Specifications
12–5