HP 1660CS-Series User Manual page 157

Logic analyzers
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The Analyzer Format Menu
Master and Slave Clock fields (State only)
Clock edges are ORed to clock edges, clock qualifiers are ANDed to clock
edges, and clock qualifiers can be either ANDed or ORed together. All clock
and qualifier combinations on the left side of the graphic line are ORed to all
combinations on the right side of the line. For example, in a six-clock model,
all combinations of the J, K, and L clock with Q1 and Q2 qualifiers, are ORed
to the clock combinations of the M, N, and P clocks with Q3 and Q4 qualifiers.
See Also
"Pod Clock Field" found earlier in this chapter for information on selecting
clocking arrangement types, such as Master, Slave, or Demultiplex.
Slave Clock field
Master Clock field
Pod clock field
Clock fields
7-38

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