HP 1660CS-Series User Manual page 155

Logic analyzers
Table of Contents

Advertisement

The Analyzer Format Menu
Pod clock field (State only)
Channel assignments are displayed as Demux Master and Demux Slave. For
easy recognition of the two sets of data, assign slave and master data to
separate labels.
When the analyzer sees a match between the slave clock input and the Slave
Clock arrangement, Demux Slave data is latched. Then, followed by a match
of the master clock and the master clock arrangement, the slave data is
strobed into analyzer memory along with the master data. If multiple slave
clocks occur between master clocks, only the most recently latched data is
strobed into analyzer memory.
Analyzer Memory
latches on Master Clock
Data on Master
Latching slave data in demultiplex mode
7-36
latches on
Slave Latch
Slave Clock
Same pod
Data on Slave

Hide quick links:

Advertisement

Table of Contents

Troubleshooting

loading

This manual is also suitable for:

1662cs1663cs1660cs1661cs

Table of Contents