HP 1660CS-Series User Manual page 154

Logic analyzers
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Master
This option specifies that data on all pods designated "Master Clock," in the
same analyzer, are strobed into memory when the status of the clock lines
match the clocking arrangement specified under the Master Clock.
See Also
"Master and Slave Clock fields" found later in this section for information
about configuring a clocking arrangement.
Slave
This option specifies that data on a pod designated "Slave Clock" is latched
when the status of the slave clock meets the requirements of the slave
clocking arrangement. Then, followed by a match of the master clock and the
master clock arrangement, the slave data is strobed into analyzer memory
along with the master data. See the figure below.
If multiple slave clocks occur between master clocks, only the data latched by
the last slave clock prior to the master clock is strobed into analyzer memory.
Latching slave data
Demultiplex
The Demultiplex mode is used to store two different sets of data that occur at
different times on the same channels. In Demultiplex mode both the master
and slave clocks are used, but only one pod of the pod pair is sampled.
Analyzer Memory
latches on Master Clock
latches on
Slave Clock
Data on Master
The Analyzer Format Menu
Pod clock field (State only)
Slave Latch
Data on Slave
7-35

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