Supplemental Characteristics (Logic Analyzer) - HP 1660 Series Service Manual

General Information

Supplemental Characteristics (logic analyzer)

Supplemental Characteristics (logic analyzer)

Pr obes Pr obes
Input Resistance
Input Capacitance
Minimum Voltage Swing
Threshold Range
St at e Anal ysi s St at e Anal ysi s
State/Clock Qualifiers
*
Time Tag Resolution
Maximum Time Count
Between States
Maximum State Tag Count
Ti mi ng Anal ysi s Ti mi ng Anal ysi s
Sample Period Accuracy
Channel-to-Channel Skew
Time Interval Accuracy
Tr i gger i ng Tr i gger i ng
Sequencer Speed
State Sequence Levels
Timing Sequence Levels
Maximum Occurrence Counter
Value
Pattern Recognizers
Maximum Pattern Width
Range Recognizers
Range Width
Timers
Timer Value Range
Glitch/Edge Recognizers
Maximum Glitch/Edge Width
*
Maximum state clock rate with time or state tags on is 100 MHz. When all pods are assigned to a state or timing machine,
time or state tags halve the memory depth.
1–6
100 kΩ, ± 2%
~ 8 pF
500 mV, peak-to-peak
± 6.0 V, adjustable in 50-mV increments
6
8 ns or 0.1%, whichever is greater
34 seconds
* 9
4.29 x 10
0.01 % of sample period
2 ns, typical
± [sample period + channel-to-channel skew
+( 0.01%) ( time reading) ]
125 MHz, maximum
12
10
1,048,575
10
136 channels in HP 1660A, 102 channels in HP 1661A,
68 channels in HP 1662A, 34 channels in HP 1663A
2
32 bits each
2
400 ns to 500 seconds
2 ( timing only)
136 channels in HP 1660A, 102 channels in HP 1661A,
68 channels in HP 1662A, 34 channels in HP 1663A