HP 1660CS-Series User Manual page 166

Logic analyzers
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2. Find too few states between event 1 and event 2
This macro becomes true when a designated pattern 1 is seen, followed by a
designated pattern 2, and with less than a selected number of states
occurring between the two patterns. It uses three or four internal sequence
levels.
3. Find too many states between event 1 and event 2
This macro becomes true when a designated pattern 1 is seen, followed by at
least a selected number of states, then followed by a designated pattern 2. It
uses two internal sequence levels.
4. Find n-bit serial pattern
This macro finds an "n" bit serial pattern on a designated channel and a
designated label. It uses "n" internal sequence levels.
Time Violations
1. Find event 2 occurring too soon after event 1
This macro becomes true when a designated pattern 1 is seen, followed by a
designated pattern 2, and with less than a selected time period occurring
between the two patterns. It uses two internal sequence levels.
2. Find event 2 occurring too late after event 1
This macro becomes true when a designated pattern 1 is seen, followed by at
least a selected time period, before a designated pattern 2 occurs. It uses two
internal sequence levels.
Delay
1. Wait "n" external clock states
This macro becomes true after a designated number of user clock states have
occurred. It uses one internal sequence level.
The Analyzer Trigger Menu
State trigger macro library
7-47

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