HP 1660CS-Series User Manual page 281

The Analyzer Hardware
Oscilloscope board theory
that of the ADC since the FISO clocks on both transitions of the clock
period. Data is buffered onto the CPU data bus for processing.
Triggering There are two main trigger circuits that control four trigger
sources. The two trigger circuits are the analog trigger and the logic
trigger. The analog trigger IC operates as a multichannel Schmidt
trigger/comparator. A trigger signal (a copy of the analog input signal)
from each of the inputs (channel 1 and channel 2) is directed to the
analog trigger IC inputs. The trigger signal is continuously compared
with the trigger reference level selected by the user. Once the trigger
condition is met, the trigger true signal is fed to the logic trigger, which
begins the acquisition and store functions by way of the time base.
The four trigger sources are Channel 1, Channel 2, Intermodule Bus (IMB),
and external BNC. Channel 1 and channel 2 triggers were discussed
previously. The IMB trigger signal is sent directly to the logic trigger.
External triggering is provided by the BNC input of the HP 1660CS-series
logic analyzer.
Time base The time base provides the sample clocks and timing
necessary for data acquisition. It consists of the 100 MHz reference
oscillator and time base hybrid.
The 100 MHz reference oscillator provides the base sample frequency.
The time base hybrid has programmable dividers to provide the rest of the
sample frequencies appropriate for the time range selected. The time base
uses the time-stretched output of the fine interpolator to time-reference the
sampling to the trigger point. The time base has counters to control how
much data is taken before (pre-trigger data) and after (post-trigger data) the
trigger event. After the desired number of pre-trigger samples has occurred,
the time base hybrid sends a signal to the logic trigger (trigger arm)
indicating it is ready for the trigger event. When the trigger condition is
satisfied, the logic trigger sends a signal back to the time base hybrid. The
time base hybrid then starts the post-trigger delay counter.
When the countdown reaches zero, the sample clocks are stopped and the
CPU is signaled that the acquisition is complete. The fine interpolator is a
dual-slope integrator that acts as a time-interval stretcher. When the logic
trigger receives a signal that meets the programmed triggering requirements,
it signals the time base. The time base then sends a pulse to the fine
interpolator. The pulse is equal in width to the time between the trigger and
the next sample clock. The fine interpolator stretches this time by a factor of
approximately 500. Meanwhile, the time base hybrid runs a counter with a
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