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STEP 5 Operations
Flip-Flop for a Latching Signal Output (reset dominant)
A" 1" at input I 0.1 sets flip-flop Q 1.0 (signal state "1"). If
the signal state at input I 0.1 changes to" 0", the state of
output Q 1.0 is maintained, i.e., the signal is latched.
A "1" at input I 0.0 resets the flip-flop (signal state 0").
When the "SET" signal (input I 0.1) and the "RESET"
signal (input I 0.0) are applied at the same time, the
scanning operation that was programmed last (in this case
A I 0.0) is in effect during processing of the rest of the
program.
In this example, resetting output Q 1.0 has priority..
STL
A
I
0.1
S
Q
1.0
A
I
0.0
R
Q
1.0
*
NOP
0
"NOP 0" is necessary if the program is to be represented in LAD or CSF form on programmers
*
NOP 0
with a screen. During programming in LAD and CSF, such "NOP 0" operations are allotted
automatically.
8-8
Example
CSF
Q 1.0
I 0.1
S
I 0.0
R Q
Circuit Diagram
I 0.0
I 0.1
Q 1.0
LAD
Q 1.0
I 0.1
S
I 0.0
R
Q
EWA 4NEB 812 6210-02
S5-95F
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