HP 3562A Service Manual page 557

MOD E L 3562A
FFT I NT E RRU PT T E ST
This test checks the abil ity of the FFT board to interru pt the main system CPU and exercises
the add ress ing and globa l bus c i rcu its. The C PU i nterrupt m u st occ u r within a l i m ited
time. Two resu lts are l isted if this test is su ccessfu l : the timeout test (ca l led the " I nterru pt
Registered" resu lts) and the exerc ise routine resu lts (cal led the "FFT I nterru pt" res u lts).
The test runs as fo l l ows:
1 .
The system CPU (A2) loads a comm and into a register on the FFT board and starts
a timer.
T h i s action uti l izes the system bus i nterface c i rcu its and the FFT interru pt c i rc u it on the
FFT board .
2 . The FFT m icroprocessor system interprets the comma nd,
3. stores two num bers (5555H and AAAA H) in the scale factor registers in gl obal RAM and
4. activates the C P U interru pt.
T h i s action uti l izes the FFT addres s i ng c i rcu itry, the global bus add ress and data inte r­
face c i rcu its, and the CPU inte rrupt c i rc u it on the FFT board .
5 . I f the system C P U rece ives the interru pt from the FFT board before the end of the
timer cyc le, the " F FT I nterrupt Reg istered" test passes.
6. The CPU checks the n u m bers stored in RAM aga i n st a known n u m ber. If the n u m bers
are identi cal, the "FFT I nterru pt" test passes.
FFT RAM T E ST
This test is a self-test run by the TMS320 FFT m icroprocessor on its own internal RAM.
The test p rogram res ides in ROM in the FFT m i croprocessor system . T he system CPU
add resses the FFT board and loads a command to run the RAM test. After the test is
com plete the FFT board interru pts the system CPU and passes the test res u lts (pass or
fail) back to the C P U .
The system interface and both the FFT and CPU inte rrupt c i rcu its are exe rcised as a by­
prod u ct of this test.
FFT ROM T E ST
E ach of the program and coefficient ROMs have a checksum n u m ber i n the last byte.
When the ROM test is run the system C P U reads the RaMs, gene rates its own checksum
and compares it with the checks u m stored i n the program and coefficie nt ROMs.
To read the contents of the FFT RaMs, the CPU sends instructions to the FFT board causing
it to p lace the ROM contents, one word at a time, into a specific location i n g l obal RAM
where the C PU can access the d ata. The FFT board changes contents of another l ocation
of gl obal RAM to zero each time it com p l etes the transfer of a word . The CPU mon itors
this second location for an i nd ication of val id data in the fi rst location.
The system and global interface b l ocks are exerc ised as a by-p rod u ct of this test.
S E RV I C E
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